Structures in which a vertical MOSFET and a free wheel diode are contained in one chip for the simplification of the structure of MOSFET used in an inverter have been conventionally proposed. (Refer to Patent Document 1, for example.) In semiconductor devices obtained by containing a vertical MOSFET and a free wheel diode in one chip, the free wheel diode is formed of a p-n junction comprised of a body layer and a drift layer provided in the vertical MOSFET.
[Patent Document 1] Japanese Unexamined Patent Publication No. 2004-22716
The above conventional configuration makes it possible to carry out diode operation without need for an external free wheel diode during inverter operation. This reduces a number of required components and brings about an advantage of the feasibility of size and cost reduction. With the above conventional configuration, however, excess carriers are discharged during diode operation and they flow out as reverse recovered charge Qrr and this poses a problem of increased recovery loss.
To solve this problem, the present applicants proposed a technique for suppressing excess carrier injection using a gate for driving MOSFET. This technique is as follows: during diode operation, a positive voltage slightly lower than the threshold value of MOSFET is applied to form a weak inversion layer to accelerate the recombination of injected excess carriers; or a depletion layer is formed to reduce an area used as a diode. (Refer to Japanese Patent Application No. 2010-6549.)
This method brings about an effect that it is possible to suppress the injection of excess carriers to reduce reverse recovered charge Qrr without increasing loss during diode operation. However, a difficulty arises because one and the same gate has charge of MOSFET operation and excess carrier injection suppressing operation. When noise enters the gate and the gate voltage fluctuates during excess carrier injection suppressing operation, there is a possibility that the threshold value of the MOSFET is readily exceeded. In this case, self turn-on occurs and the MOSFET is unintentionally turned on.
In the above description, a vertical MOSFET has been taken as an example of the semiconductor switching element with an insulated gate structure. However, the above problems arise also in any vertical MOSFET including trench gate type, planar type, and concave type and the horizontal MOSFETs also involve the same difficulties. The same difficulties arise also in vertical and horizontal IGBTs. These difficulties arise not only in semiconductor devices in which a semiconductor switching element with an insulated gate structure and a free wheel diode are contained in one chip. They arise also in those in which a semiconductor switching element and a free wheel diode are formed in different chips as long as they are semiconductor devices so structured that a semiconductor switching element with an insulated gate structure and a free wheel diode are coupled in parallel. Also when a semiconductor switching element and a free wheel diode are formed in different chips, the above excess carrier injection suppression can be implemented. Even when this technique is applied, however, recovery measures can be carried out but the difficulty of self turn-on still remains.
Systems with the following structure have been conventionally adopted: a structure in which IGBT as a semiconductor switching element used in an inverter for driving an electric induction load such as a motor and a free wheel diode (hereafter, abbreviated as FWD) are formed in different chips and they are coupled in parallel. To further reduce the size of these systems, the following practice has been taken: IGBT is replaced with a vertical MOSFET and a body diode incorporated in the vertical MOSFET is caused to function as FWD.
In case of structures in which a vertical MOSFET and FWD are contained in one chip, injection efficiency is intentionally reduced by controlling minority carrier life or taking other like measures to reduce the recovery loss of the FWD. In this case, conversely, on-voltage during back flow operation is raised and this increases back flow loss. Therefore, a difficulty in achieving both recovery loss reduction and back flow loss reduction arises.
To cope with this, the technology for implementing the following is disclosed in Patent Document 2: a deep trench gate is formed in a diode region where the injection efficiency is low in a chip in which a semiconductor switching element is formed; during back flow operation, a negative bias is applied to the trench gate to form an accumulation layer in a vicinal region to enhance injection efficiency and reduce on-voltage.
[Patent Document 2] Japanese Unexamined Patent Publication No. 2009-170670
However, structures in which a deep trench gate is formed in a diode region as described in Patent Document 2 involve a difficulty. It is necessary to form a trench gate for diode region different in depth from the trench gate for forming a semiconductor switching element. For this reason, a process for forming the trench gate different in depth is required and this incurs increase in the number of manufacturing process steps and increase in manufacturing cost.